The present invention relates to a method of driving a liquid crystal display device for use in a personal computer, a work station or the like, and more specifically to a technology effective for application to a video signal line driver of a liquid crystal display device to enable a multi-gray scale display.
Liquid crystal display devices of the prior art are broadly classified into a simple matrix type liquid crystal display device wherein a pixel at an intersection of X and Y stripe electrodes is driven, and an active matrix type liquid crystal display device wherein a pixel is driven by switching an active element (for example, a thin film transistor) provided at each pixel.
An active matrix type liquid crystal display device has an advantage that, since a liquid crystal (hereinafter LC) driving voltage (gray scale voltage) is applied to a pixel electrode via an active element, for example, a thin film transistor (TFT), no crosstalk occurs between pixels and this eliminates the need for a special driving scheme to prevent crosstalk as required in the case of a simple matrix type liquid crystal display device and provides a multi-gray scale display.
Display methods of the active matrix type liquid crystal display device are broadly classified into the following two types.
One of the two types produces a display by driving an LC layer sandwiched between a pair of substrates each having transparent electrodes on its inner surface with an electric field generated by an LC driving voltage applied between the opposing transparent electrodes of the substrates and substantially perpendicular to the substrates, and modulating the amount of light passing through the LC layer after passing through one of the opposing transparent electrodes, and this type is hereinafter referred to as a vertical electric field type.
The other produces a display by driving an LC layer sandwiched between a pair of substrates with an electric field generated by an LC driving voltage applied between two electrodes on the same substrate or the two substrates and substantially parallel with the surfaces of the substrates, and modulating the amount of light passing through the LC layer after passing through the space between the two electrodes, and this type is hereinafter referred to as in-plane switching type.
FIG. 13 is a block diagram showing a schematic configuration of an active matrix type liquid crystal display module which is an active matrix type liquid crystal display device of the conventional vertical electric field type.
In FIG. 13, a liquid crystal display panel (TFT-LCD) is a liquid crystal display panel of the color TFT (Thin Film Transistor) type and has 640.times.3.times.480 pixels.
A drain driver (video signal line driver) 530 is disposed at the top of the liquid crystal display panel (TFT-LCD), and all of the video signal lines (drain signal lines or vertical signal lines) (DL) of the liquid crystal display panel (TFT-LCD) are connected to the drain driver 530.
Also a gate driver (vertical scanning circuit) 540 and an interface circuit 500 are disposed at the sides of the liquid crystal display panel (TFT-LCD), and each scanning signal line (gate signal line or horizontal signal line) (GL) of the liquid crystal display panel (TFT-LCD) is connected to the gate driver 540.
FIG. 14 is a diagram showing an equivalent circuit of the liquid crystal display panel (TFT-LCD) shown in FIG. 13.
FIG. 14 is a circuit diagram, and is illustrated corresponding to the actual geometric arrangement, and in FIG. 14, AR designates a display matrix area.
Each pixel of the liquid crystal display panel (TFT-LCD) is disposed within a region enclosed by two adjacent scanning signal lines (GL) and two adjacent video signal lines (DL), and includes two thin-film transistors (TFT1, TFT2), a pixel electrode (ITO1) and an additional storage capacitor (Cadd).
All drain electrodes of TFTs (TFT1's and TFT2's) associated with pixels in each column among pixels arranged in a matrix are connected to a corresponding video signal line (DL), which in turn is connected to a drain driver 530 for supplying an LC driving voltage (gray scale voltage) to a pixel electrode (ITO1) to drive the LC layer.
All gate electrodes (GT) of TFTs (TFT1's and TFT2's) associated with pixels in each row among pixels arranged in a matrix are connected with a corresponding scanning signal line (DL), which in turn is connected to a gate driver 540 for supplying a positive or negative bias voltage to the gate electrodes of the TFTs (TFT1's and TFT2's) during a horizontal scan period.
Source electrodes of thin film transistors (TFT1, TFT2) of a pixel are connected to a pixel electrode (ITO1), and an LC layer between the pixel electrode (ITO1) and a common electrode (ITO2) produces a capacity (CLC) connected to the pixel electrode (ITO1).
Each of the thin film transistors (TFT1, TFT2) becomes conducting when a positive bias voltage is applied to the gate electrode, and it becomes non-conducting when a negative bias voltage is applied to the gate electrode.
Also an additional storage capacitor (Cadd) is connected between each pixel electrode (ITO1) and a capacitor signal line (Cn).
As known well, the additional storage capacitor (Cadd) acts to reduce influence of the potential change of the gate electrode (GT) on the pixel electrode (ITO1) when each of the thin film transistors (TFT1, TFT2) performs switching.
The additional storage capacitor (Cadd) acts also to increase the time constant of discharge, and stores the video information for a long time after each of the thin film transistors (TFT1, TFT2) is turned off.
In addition, the capacitor signal line (Cn) may be shared by a scanning signal line (GL) immediately above the scanning line associated with the pixel under consideration.
An interface circuit 500 shown in FIG. 13 comprises a display control circuit 510 and a power supply circuit 520, and is formed as one driver circuit board (interface board).
The display control circuit 510 is formed as one semiconductor integrated circuit (LSI), and controls and drives a drain driver 530 and a gate driver 540 based on control signals such as a clock signal, a display timing signal, a horizontal sync signal, and a vertical sync signal and a display signal transmitted from the main computer.
If a display timing signal is inputted, the display control circuit 510 judges this as a display start position, and outputs a row of the received display data through a bus line 533 of the display data to the drain driver 530.
Then the display control circuit 510 outputs a display data latch clock (D2) which serves as a display control signal for latching display data, through a signal line 531 to a data latch circuit of the drain driver 530.
In this case, the display data from the main computer are transferred in pixel units comprising a triad of data for red (R), green (G) and blue (B) per unit time. Each display data is comprised of 18 bits, six bits per color.
Further, a carry output from the drain driver 530 in one stage is inputted as a carry input to the drain driver 530 in the next stage, and latching operation of the data latch circuit of the drain driver 530 is controlled by the carry signal to prevent wrong display data from being written into the data latch circuit.
When inputting of the display timing signal is finished or when a predetermined time has elapsed after the display timing signal is inputted, the display control circuit 510 determines that the display data corresponding to a horizontal scanning line have been inputted, and outputs an output timing control clock (D1) which serves as a display control signal for outputting the display data stored in the latch circuit of the drain driver 530 to a video signal line (DL) of a liquid crystal display panel (TFT-LCD), to the drain driver 530 through a signal line 532.
When the first display timing signal is inputted after the vertical sync signal is inputted, the display control circuit 510 judges this as the first display line and outputs a frame start indicating signal through a signal line 542 to the gate driver 540.
Further, the display control circuit 510 outputs a shift clock (G) of a horizontal scanning period through a signal line 541 to the gate driver 540 based on the horizontal sync signal so that a positive bias voltage is applied to each scanning signal line (GL) of the liquid crystal display panel (TFT-LCD) in sequence per horizontal scanning period.
Thereby a plurality of thin film transistors (TFT1, TFT2) connected to each scanning signal line (GL) of the liquid crystal display panel (TFT-LCD) become conducting during a horizontal scanning period.
The power supply circuit 520 comprises a voltage generating circuit 523 and a gate voltage generating circuit 524, and the gate voltage generating circuit 524 generates drive voltages (positive and negative bias voltages) to be applied to gates of the thin film transistors (TFT1, TFT2).
The voltage generating circuit 523 is comprised of a voltage divider formed of resistors connected in series, and generates nine gray scale reference voltages (V0-V8).
FIG. 15 is an exploded perspective view showing components of the active matrix type liquid crystal display module shown in FIG. 13.
In FIG. 15, SHD designates a frame-shaped shield case (metal frame) made of sheet metal, LCW designates a display window of the shield case (SHD), SPB designates a light diffuser, LCB designates a light guide, RM designates a reflector, BL designates a backlighting fluorescent lamp, and LCA designates a backlight case.
Driver circuit boards (PCB1, PCB2) are mounted around the liquid crystal display panel (TFT-LCD).
The driver circuit boards (PCB1, PCB2) are disposed along the periphery of the liquid crystal display panel, and the individual driver circuit boards (PCB1, PCB2) are electrically connected to other circuits by flat cables (not shown).
The driver circuit board (PCB1) has electronic parts thereon such as tape carrier packages (TCP), capacitors or the like, and is divided into the drain driver 530 portion and the gate driver 540 portion.
The driver circuit board (PCB2) has electronic parts thereon, such as semiconductor integrated circuits (IC), capacitors, resistors or the like, and the driver circuit board (PCB2) constitutes an interface circuit shown in FIG. 13.
The shield case (SHD), the liquid crystal display panel (TFT-LCD) with the driver circuit boards (PCB1, PCB2) mounted on its periphery , the light diffuser (SPB), the light guide (LCB), the reflector (RM), the backlighting fluorescent lamp (BL) and the backlight case (LCA) are stacked in the arrangement relation shown in FIG. 15 to form the active matrix type liquid crystal display module.
The active matrix type liquid crystal module is assembled as a unit by clamping its parts with claws and hooks provided in the shield case (SHD).
The backlight case (LCA) is configured to house the backlighting fluorescent lamp (BL), the light diffuser (SPB), the light guide (LCB) and the reflector (RM). Light from the backlighting fluorescent lamp (BL) disposed at the side of the light guide (LCB) is made uniform on the display screen by the light guide (LCB), the reflector (RM) and the light diffuser (SPB) and then is projected toward the liquid crystal display panel (TFT-LCB).
An inverter circuit board (PCB3) is connected to the backlighting fluorescent lamp (BL) and serves as a power source of the backlighting fluorescent lamp (BL).
The illuminating light from the backlighting fluorescent lamp (BL) passes through a polarizer on the backlight side, the liquid crystal layer (LC) filled and sealed between a pair of glass substrates and the front polarizer, and then exits from the liquid crystal display panel (TFT-LCD).
An area of the display window (LCW) of the shield case (SHD) defines a display area of the active matrix type liquid crystal display module, and a region other than the display area of the active matrix type liquid crystal display module, that is, a peripheral region around the display window of the shield case (SHD) is usually called a frame border area.
As shown in FIG. 16, the liquid crystal layer (LC) changes light transmission according to the strength of an electric field across the LC layer perpendicular to the upper and lower glass substrates.
A multi-gray scale image can be produced on the LC display panel by varying a voltage applied between a common electrode (ITO2) on one of a pair of glass substrates and a pixel electrode (ITO1) on the other of the pair, specifically, by applying to a pixel electrode (ITO1) an LC driving voltage corresponding to one of a plurality of gray scale levels with respect to a voltage applied to the common electrode (ITO2), consequently by modulating the amount of light passing through the LC layer from the backlighting fluorescent lamp and changing the amount of light passing through the front polarizer.
In general, when a voltage of the same polarity (DC voltage) is left applied across the LC for a long time, inclination of liquid crystal molecules in the liquid crystal layer (LC) becomes fixed. As a result, image retention occurs and shortens the lifetime of the LC.
In order to prevent this, in a conventional liquid crystal display device, the polarity of the LC driving voltage applied across the LC layer is reversed periodically. Specifically, the LC driving voltage applied to the pixel electrode is changed from positive to negative, and vice versa, every period with respect to the LC driving voltage applied to the common electrode.
For applying alternating voltages across the LC layer, two methods, a fixed common-electrode voltage method and a common-electrode voltage inversion method, are known as shown in FIGS. 17A and 17B, respectively.
The common-electrode voltage inversion method reverses both voltages applied to the common electrode and the pixel electrode, respectively, and the fixed common-electrode voltage method reverses the polarity of the voltage applied to the pixel electrode with respect to the fixed common voltage periodically. electrode.
The fixed common-electrode voltage method has disadvantages that an amplitude of a voltage applied to the pixel electrode is twice that of the common-electrode voltage inversion method and a low voltage driver cannot be used in this method, but has advantages that a dot-inversion drive method or a column-inversion drive method (See SID 91 DIGEST pp. 551-554 for further details) provides power consumption saving and an excellent quality display.
The active matrix type liquid crystal display module shown in FIG. 13 employs the dot-inversion drive method.
FIG. 18 is a diagram showing a relationship between the LC driving voltage outputted from the drain driver 530 to the video signal line (DL) shown in FIG. 13, i.e., the LC driving voltage applied to the pixel electrode (ITO1) and the LC driving voltage applied to the common electrode (ITO2).
In FIG. 18, the LC driving voltage outputted from the drain driver 530 to the video signal line (DL) is illustrated as displaying black on a white background of the liquid crystal display panel(TFT-LCD).
As shown in FIG. 18, the LC driving voltage (VDH) outputted from the drain driver 530 to the odd-numbered video signal line (DL) and the LC driving voltage (VDL) outputted from the drain driver 530 to the even-numbered video signal line (DL) are opposite in polarity with respect to the LC driving voltage (VCOM) applied to the common electrode (ITO2). That is, if the LC driving voltage (VDH) outputted to the odd-numbered video signal line (DL) is positive (or negative) in polarity, the LC driving voltage (VDL) outputted to the even-numbered video signal line (DL) is negative (positive) in polarity.
The polarity is inverted every line, and further, the polarity of every line is inverted every frame.
By using the dot-inversion drive method, since voltages applied to the adjacent signal lines (DL) are opposite from each other in polarity, currents flowing through the common electrode (ITO2) or the gate electrode (GT) cancel out each other and the power consumption can be reduced.
Also since a current flowing through the common electrode (ITO2) is small resulting in a small voltage, the voltage level of the common electrode (ITO2) is stable and deterioration of the display quality can be minimized.
FIG. 19 is a block diagram showing a schematic configuration of the drain driver 530 shown in FIG. 13.
As shown in FIG. 19, the drain driver 530 has a gray scale voltage generating circuit 551, which generates 64 levels of gray scale voltages based on nine gray scale reference voltages (V0-V8) inputted from the voltage generating circuit 523 and outputs the gray scale voltages through a voltage bus line 558 to an output circuit 557.
A shift register 553 within a control circuit 552 of the drain driver 530 generates a data input control signal for an input register 554 based on the display data latch clock (D2) inputted from the display control circuit 510 and outputs the data input control signal to an input register 554.
The input register 554 latches display data of six bits per color corresponding to its output signals in number, in synchronization with the display data latch clock (D2) inputted from the display control circuit 510 based on the data input control signal outputted from the shift register 553.
A storage register 555 latches display data in the input register 554 in response to the output timing control clock (D1) from the display control circuit 510 (FIG. 13).
The display data inputted to the storage register 555 are inputted through a level shifter circuit (1) 556 to an output circuit 557.
A control signal for AC driving to the drain driver 530 is used to control the polarity of a voltage outputted to the video signal line (DL).
FIG. 20 is a block diagram explaining a configuration of the drain driver 530, centering on a configuration of the output circuit 557 shown in FIG. 19.
The output circuit 557 shown in FIG. 19 is comprised of a decoder circuit (1) 561, an amplifier circuit pair 563, a switching circuit (1) 562 for switching between inputs of the amplifier circuit pair 563 and a switching circuit (2) 564 for switching between outputs of the amplifier circuit pair 563.
Reference characters Y1, Y2, Y3 and Y4 designate first, second, third and fourth video signal lines respectively, and a data latch circuit 565 indicates the input register 554 and the storage register 555 shown in FIG. 19.
A decoder circuit (1) 561 is comprised of a decoder circuit 577 for selecting a gray scale voltage corresponding to the display data outputted from each data latch circuit 565 (specifically the storage register 555 shown in FIG. 19), among 64 levels of gray scale voltages outputted from the gray scale voltage generating circuit 551 through the voltage bus lines 558 shown in FIG. 19.
The decoder circuit 577 is provided for each data latch circuit 565, and is a complementary decoder circuit formed of PMOS and NMOS transistors.
An amplifier circuit pair 563 is provided for each pair of adjacent decoder circuits 577, and is formed of a high-voltage inverting amplifier 571 and a low-voltage rail-to-rail amplifier 572.
The high-voltage inverting amplifier 571 outputs an LC drive voltage of positive polarity, and the low-voltage rail-to-rail amplifier 572 outputs an LC drive voltage of negative polarity.
The switching circuit (1) 562 inputs two gray scale voltages outputted from two decoder circuits 577 corresponding to two adjacent video signal lines (DL), for example, the two decoder circuits 577 corresponding to the first video signal line Y1 and the second video signal line Y2, respectively, to the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572 of the amplifier circuit pair 563, respectively and alternately.
The switching circuit (2) 564 supplies two output voltages outputted from the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572 of the amplifier circuit pair 563 to a proper one of two adjacent video signal lines (DL), for example, the first video signal line Y1 and the second video signal line Y2, respectively, in synchronization with the switching circuit (1) 562.
Here, the switching circuit (1) 562 and the switching circuit (2) 564 are controlled based on the control signal (M) for AC driving.
With the dot-inversion drive method, two voltages applied to adjacent signal lines (DL), for example, the first video signal line Y1 and the second video signal line Y2 ,or the third video signal line Y3 and the fourth video signal line Y4, are opposite in polarity.
In the output circuit 577 shown in FIG. 19, the switching circuit (1) 562 inputs two gray scale voltages outputted from decoder circuits (1) 561 corresponding to two adjacent video signal lines as shown in FIG. 20, for example, the first video signal line Y1 and the second video signal line Y2, to the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572, respectively and alternately. The switching circuit (2) 564 supplies the two output voltages outputted from the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572 to a proper one of the two adjacent video signal lines (DL), for example, the first video signal line Y1 and the second video signal line Y2, respectively in synchronization with the switching circuit (1) 562.
That is, the control signal (M) for AC driving switches between the following state 1 and state 2.
State 1
Decoder circuit 577 output corresponding to signal line Y1.fwdarw.High-voltage inverting amplifier.fwdarw.Signal line Y1 Decoder circuit 577 output corresponding to signal line Y2.fwdarw.Low-voltage rail-to-rail amplifier.fwdarw.Signal line Y2
State 2
Decoder circuit 577 output corresponding to signal line Y1.fwdarw.Low-voltage rail-to-rail amplifier.fwdarw.Signal line Y1 Decoder circuit 577 output corresponding to signal line Y2.fwdarw.High-voltage inverting amplifier.fwdarw.Signal line Y2
When the drain driver 530 shown in FIG. 20 is employed, a pair of the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572 need not be provided for each video signal line (DL), a chip area of a semiconductor integrated circuit (IC chip) constituting the drain driver 530 may be reduced in comparison with an IC wherein a pair of the high-voltage inverting amplifier 571 and the low-voltage rail-to-rail amplifier 572 are provided for each video signal line (DL).
FIG. 21 is a circuit diagram showing a circuit configuration of the decoder circuit 577 shown in FIG. 20.
The decoder circuit 577 has 64 transistor rows (TRP1), each row comprising six low-voltage PMOS transistors connected in series on one side of an output terminal and six low-voltage NMOS transistors connected in series on the other side of the output terminal.
64 levels of gray scale voltages outputted from the gray scale voltage generating circuit 551 through the voltage bus lines 558 shown in FIG. 19 are applied between ends of the 64 transistor rows (TRP1), respectively.
A predetermined combination of non-inverted (T) and inverted (B) outputs of each bit of six bits for display data are outputted from the level shift circuit (1) 556 and applied selectively to each of the gate electrodes of the six PMOS transistors and the six NMOS transistors of each transistor row (TRP1).
FIG. 22 is a circuit diagram showing a circuit configuration of the switching circuit (1) 562, the amplifier circuit pair 563 and the switching circuit (2) 564 shown in FIG. 20.
In FIG. 22, switching circuits (IN1, IN2) indicate the switching circuit (1) 562 in FIG. 20, and switching circuits (OUT1, OUT2) indicate the switching circuit (2) 564 in FIG. 20.
Here, the switching circuits (IN1, IN2) are formed of complementary MOS transistors comprising PMOS and NMOS transistors connected in parallel.
The low-voltage rail-to-rail amplifier 572 constituting the amplifier circuit pair 563 is a voltage follower wherein an inverting terminal and an output terminal of an operational amplifier (OP1) are directly connected, and a non-inverting terminal is made as an input terminal.
The high-voltage inverting amplifier 571 constituting the amplifier circuit pair 563 is an inverting amplifier comprising an operational amplifier (OP2), and a switching circuit (SW1) is connected between an inverting input terminal and an output terminal of the operational amplifier (OP2), and a capacitor (C2) is connected between an inverting input terminal and the output terminal of the operational amplifier (OP2) through a switching circuit (SW2), and one terminal of a capacitor (C1) is connected to the inverting input terminal of the operational amplifier (OP2).
A reference voltage (Vcen) is applied to the non-inverting input terminal of the operational amplifier (OP2), and is applied through a switching circuit (SW3) to the other terminal of the capacitor (C1) and applied through a switching circuit (SW4) to one terminal of the capacitor (C2) on the side connected to the switching circuit (SW2).
Here, the reference voltage (Vcen) is also the potential of the LC driving voltage (Vcom) applied to the common electrode (ITO2).
In the inverting amplifier, during the reset operation, the switching circuit (SW1), the switching circuit (SW3) and the switching circuit (SW4) are turned on, and the switching circuit (SW2) is turned off. In this state, the operational amplifier (OP2) serves as a voltage follower and the potential of the output terminal and the inverting input terminal of the operational amplifier (OP2) becomes the reference voltage (Vcen), further the reference voltage (Vcen) is applied to other terminal of the capacitor (C1) and to the terminal on the side thereof connected to the switching circuit (SW2) and the capacitor (C1) and the capacitor (C2) are reset.
In the normal state, the switching circuit (SW1), the switching circuit (SW3) and the switching circuit (SW4) are turned off and the switching circuit (SW2) is turned on, and the gray scale voltage inputted through the capacitor (C1) is inverted and amplified with respect to the reference voltage (Vcen).
In the liquid crystal display device such as an active matrix type liquid crystal display module, the display area has been large-sized and for enhancement of aesthetic appeal of the display device and elimination of an unavailable space, it is required that an area other than the display area in the liquid crystal display device, that is, a frame border area is made as small as possible.
Therefore in the active matrix type liquid crystal display module shown in FIG. 13, the drain driver 530 is disposed on one side of the liquid crystal display panel (TFT-LCD) so that frame border area may be made small.
In the drain driver 530 of the active matrix type liquid crystal display module shown in FIG. 13, however, since a gray scale voltage inputted to the high-voltage inverting amplifier 571 or the low-voltage rail-to-rail amplifier 572 is switched by the switching circuit (1) 562, a large number of the switching circuits (IN1, IN2) constituting the switching circuit (1) shown in FIG. 22 are required, and are an obstacle to reduction of the frame border area of the liquid crystal display panel (TFT-LCD)
The high-voltage inverting amplifier 571 requires switch circuits (SW1-SW4) (FIG. 22) and a controller circuit for controlling the switch circuits (SW1-SW4), and increases a chip size of a semiconductor integrated circuit (IC chip) is an obstacle to reduction of the frame border area of the liquid crystal display panel (TFT-LCD).
The high-voltage inverting amplifier 571 includes capacitors (C1) and (C2) connected in series between its output terminal and the switches (IN1, IN2) and causes a problem that an unwanted current flows from the output terminal to the gray scale voltage generating circuit 551 and varies the level of the multi-gray scale voltages generated in the gray scale voltage generating circuit 551.
In order to solve the above-mentioned problems, for example, a voltage follower may be used as the high-voltage inverting amplifier 571, as in a low-voltage rail-to-rail amplifier 572. But the decoder circuit (1) 561 must be formed by high-voltage MOS transistors.
However, since the decoder circuit (1) formed of the high-voltage PMOS transistors and the high-voltage NMOS transistors requires a large area in the semiconductor integrated circuit, a chip size of the semiconductor integrated circuit (IC chip) constituting the drain driver 530 becomes large, and is an obstacle to reduction of the frame border area in the liquid crystal display panel (TFT-LCD).
Further, since the liquid crystal layer (LC) has a .gamma. characteristic as shown in FIG. 16, the LC driving voltage applied to the pixel electrode (ITO1) must be different depending on the polarity of the LC driving voltage applied to the pixel electrode (ITO1). In the drain driver 530 of the active matrix type liquid crystal display module shown in FIG. 13, however, this is not considered at all.